On reset, 0 -> PC 16 GP regs, R0 - R15, 16 bits wide 1 PC, 15 bits wide (all addresses are 15 bits) I register points to first avail dynamic-assignment (stack) reg, so top-of-stack is RF[I-1]. L register is set to highest register usable by stack assignment. 0 trap (PC -> R15; 1 -> PC) 1 trap 2 trap 3 trap 4 skz Ra (if Ra==0, PC+=2 [3 if ldim next]) 5 skn Ra (if Ra<0, PC+=2 [3 if ldim next]) 6 jr Ra (Ra -> PC) 7 il Ra (I, L <-> Ra[0:3], Ra[4:7]) (not effective for I-mode insns for 4 cycles: xch happens in ALU stage) 8 add Ra, Rb (Ra + Rb -> Ra) 9 sub Ra, Rb (Ra - Rb -> Ra) 10 and Ra, Rb (Ra & Rb -> Ra) 11 or Ra, Rb (Ra | Rb -> Ra) 12 ld Ra, Rb (Mem[Rb] -> Ra) 13 st Ra, Rb (Ra -> Mem[Rb]) 14 ldim Ra (Mem[PC+1] -> Ra; PC+=2) 15 ldpc Ra (PC -> Ra) 16 srl Ra (Ra >>= 1) 17 sll Ra (Ra <<= 1) 18 xor Ra, Rb (Ra ^ Rb -> Ra) 19 not Ra (~Ra -> Ra) 20 mov Ra, Rb (Rb -> Ra) 21 movb Ra, Rb (Rb -> Ra; Rb has permanent absolute-reg mode) 22 mova Ra, Rb (Rb -> Ra; Ra has permanent absolute-reg mode) 23 high Ra (Ra | 0x7000 -> Ra) 24 addi Ra, im (Ra + im -> Ra; im in Rb-field) 25 subi Ra, im (Ra - im -> Ra; im in Rb-field) 26 andi Ra, im (Ra & im -> Ra; im in Rb-field) 27 ori Ra, im (Ra | im -> Ra; im in Rb-field) 28 finish 32 - 63 jmp (imm -> PC) insn: op[6] i[2] Ra[4] Rb[4] jmp : op[1] imm[15] ldu : op[2] imm[14] I-field: 00 -> absolute regs (Ra and Rb fields), 16-bit ALU 01 -> Ra is Ra+I, Rb is Rb+I, no I change , 12-bit ALU 10 -> Ra is Ra+I, Rb is Rb+I, I++ after insn, 12-bit ALU 11 -> Ra is Ra+I, Rb is Rb+I, I-- after insn, 12-bit ALU Stack traps: when (Ra+I > I or Rb+I > I) and I-field == 01 or 11, underflow (2 -> PC) when I==L and I-field == 10, overflow (3 -> PC)