insn: xxxx | xxxx | xxxx | xxxx  (R-type)
       op     rC     rA     rB
      xxxx | xxxx | xxxx   xxxx  (K8-type)
       op     rC        K8
      xxxx | xxxx | xxxx | xxxx  (K4-type)
       op     rC     rA     K4

op = 0: LD rC, K8  (load-at-immediate)
        RF[rC] = DMem[K8]

op = 1: ST rC, K8  (store-at-immediate)
        DMem[K8] = RF[rC]

op = 2: ADD rC, rA, rB (addition)
        RF[rC] = RF[rA] + RF[rB]

op = 3: LDC rC, K8 (load-constant)
        RF[rC] = SignExtend(K8)

op = 4: SUB rC, rA, rB (subtraction)
        RF[rC] = RF[rA] - RF[rB]

op = 5: JMPZ rC, K8 (jump-if-zero)
        if(RF[rC] == 0) PC = PC + SignExtend(K8)

op = 6: JMPN rC, K8 (jump-if-negative)
        if(RF[rC][15] == 1) PC = PC + SignExtend(K8)

op = 7: JMP K8 (jump)
        PC = PC + SignExtend(K8)

op = 8: MUL rC, rA, rB (multiply)
        RF[rC] = RF[rA] * RF[rB]

op = 9: DIV rC, rA, rB (divide)
        RF[rC] = RF[rA] / RF[rB]

op = 10: MOD rC, rA, rB (modulus)
        RF[rC] = RF[rA] % RF[rB]

op = 11: END
        [simulation completes]

op = 13: LDR rC, K4(rB) (load-at-register)
        RF[rC] = DMem[RF[rB] + SignExtend(K4)]

op = 14: STR rC, K4(rB) (store-at-register)
        DMem[RF[rB] + SignExtend(K4)] = RF[rC]