I received my PhD in Electrical & Computer Engineering (and a brief postdoc in Computer Science) at Carnegie Mellon University in Pittsburgh, Pennsylvania, where I studied compilers, static and dynamic analysis. These days I am interested in all things related to compilers and programming language design, and how we can design compilers, runtimes, languages, and tooling to enable humans to more easily build secure, high-performance systems. I don't publish much any more, though I plan to try to continue talking about interesting work via my blog here.

See my CV for more details.

Academic Life

While at CMU, I worked with Prof. Todd Mowry and Prof. Phil Gibbons on static and dynamic program analysis with a focus on auto-parallelization and other macro-scale program transforms. I was affiliated with PDL (Parallel Data Lab) and CALCM (Computer Architecture Lab at Carnegie Mellon). Previously, in another research group, I worked on core microarchitecture (energy-efficiency and heterogeneity) and on-chip interconnect networks and memory systems.

I defended my PhD thesis in February 2019, titled Finding and Exploiting Parallelism with Data-Structure-Aware Static and Dynamic Analysis.

I was fortunate to be supported by an NSF Graduate Research Fellowship from 2010 to 2013 and an SRC Graduate Fellowship in 2009—2010. I was head graduate TA for 18-447, Intro to Computer Architecture, in Spring 2012 and 18-742, Parallel Computer Architecture, in Spring 2010.

Research Career Timeline

• Mar 2019 — Jun 2019. Postdoc in Computer Science at Carnegie Mellon University in Pittsburgh, Pennsylvania, working with Profs. Todd Mowry and Phil Gibbons.

• Jun 2015 — Feb 2019. Ph.D. in ECE at Carnegie Mellon University in Pittsburgh, Pennsylvania, working with Profs. Todd Mowry and Phil Gibbons.

• Aug 2009 — Jul 2013. Ph.D. student in ECE at CMU, working with Prof. Onur Mutlu on computer architecture topics, including energy-efficient core microarchitecture, memory systems, and on-chip interconnects. Left with Masters to work in industry (and subsequently returned).

Publications

Ph.D. Dissertation

• Chris Fallin. Finding and Exploiting Parallelism with Data-Structure-Aware Static and Dynamic Analysis. Ph.D. dissertation, defended Feb. 1, 2019.

  [ pdf ]

Invited Talks

• Chris Fallin. "wevaling the wasms: AOT JS Compilation (Or: Stuffing a Dynamic Language onto a Very Static Platform)." Wasm Research Day 2024, hosted by CMU, Pittsburgh, PA. [ video ]

• Chris Fallin. "ægraphs: Acyclic E-graphs for Efficient Optimization in a Production Compiler". Invited keynote at EGRAPHS 2023 (workshop affiliated with PLDI), Orlando, FL, June 2023.

  [ slides (pdf) | video ]

Seminar Talks

• Chris Fallin. "wevaling the wasms: AOT JS Compilation (Or: Stuffing a Dynamic Language onto a Very Static Platform)." Talk while visiting CMU, Pittsburgh, PA, and Northeastern PRL seminar, Boston, MA, April 2024.

  [ slides (pdf) | video (CMU talk) ]

Preprints

• Chris Fallin, Maxwell Bernstein. Partial Evaluation, Whole-Program Compilation. Preprint, Nov 2024.

  [ arXiv pdf ]

Conference Papers

• Alexa VanHattum, Monica Pardeshi, Chris Fallin, Adrian Sampson, Fraser Brown. Lightweight, Modular Verification for WebAssembly-to-Native Instruction Selection. In ASPLOS 2024, San Diego, CA, Apr 2024.

  [ pdf ]

• Shravan Narayan, Tal Garfinkel, Mohammadkazem Taram, Joey Rudek, Daniel Moghimi, Evan Johnson, Chris Fallin, Anjo Vahldiek-Oberwagner, Michael LeMay, Ravi Sahita, Dean Tullsen, Deian Stefan. Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI. In ASPLOS 2023, Vancouver, BC, Canada, March 2023.

  [ pdf ]

• Chris Fallin. Safe, Flexible Aliasing with Deferred Borrows. In ECOOP 2020, Virtual Conference (was Berlin, Germany), Nov 15-17, 2020.

  [ pdf ]

• Chris Fallin, Chris Wilkerson, Onur Mutlu. The Heterogeneous Block Architecture. In ICCD 2014, Seoul, South Korea, Oct 2014.

  [ pdf | slides (ppt) | IEEE Xplore ]

• Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Chang, Greg Nazario, Reetuparna Das, Gabriel Loh, Onur Mutlu. Design and Evaluation of Hierarchical Rings with Deflection Routing. In SBAC-PAD 2014, Paris, France, Oct 2014.

  [ pdf | slides (pptx) | IEEE Xplore ]

• Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA-41, Minneapolis, MN, Jun 2014.

  [ pdf | ACM DL ]

• Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, Todd C. Mowry. RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization. In MICRO-46, Davis, CA, Dec 2013.

  [ pdf | ACM DL ]

• Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu. HAT: Heterogeneous Adaptive Throttling for On-Chip Networks. In SBAC-PAD 2012, New York, NY, Oct 2012.

  [ pdf | IEEE Xplore ]

• George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, Srinivasan Seshan. On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects. In SIGCOMM 2012, Helsinki, Finland, Aug 2012.

  [ pdf | ACM DL ]

• Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu. MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect. In NOCS 2012, Lyngby, Denmark, May 2012.

  [ pdf | slides (pptx) | slides (pdf) | IEEE Xplore ]

  One of five papers nominated for the Best Paper Award by the Program Committee.

• Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Jose A. Joao, Onur Mutlu, Yale Patt. Parallel Application Memory Scheduling. In MICRO-44, Porto Alegre, Brazil, Dec 2011.

  [ pdf | slides (pptx) | ACM DL ]

• Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, Onur Mutlu. Memory Power Management via Dynamic Voltage/Frequency Scaling. In ICAC-8, Karlsruhe, Germany, Jun 2011.

  [ pdf | slides (pptx) | slides (pdf) | ACM DL ]

• Chris Fallin, Chris Craik, Onur Mutlu. CHIPPER: A Low-complexity Bufferless Deflection Router. In HPCA-17, San Antonio, TX, Feb 2011.

  [ pdf | techreport pdf | slides (pptx) | ACM DL ]

• George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu. Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need?. In Hotnets 2010, Monterey, CA, Oct 2010.

  [ pdf | slides (ppt) slides (key) | ACM DL ]

Book Chapters

• Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu. Bufferless and Minimally-Buffered Deflection Routing. In Routing Algorithms in Networks on-Chip, pp. 241—275, Springer, 2014.

Technical Reports

• Chris Fallin, Chris Wilkerson, Onur Mutlu. The Heterogeneous Block Architecture. SAFARI Technical Report No. 2014-001. March 13, 2014.

  [ pdf ]

• Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu. MinBD: A Minimally-Buffered Deflection Router Approaching Conventional Buffered-Router Performance. SAFARI Technical Report No. 2011-008. September 13, 2011.

  [ pdf ]

• Chris Fallin, Xiangyao Yu, Greg Nazario, Onur Mutlu. A High-Performance Hierarchical Ring On-Chip Interconnect with Low-Cost Routers. SAFARI Technical Report No. 2011-007. September 6, 2011.

  [ pdf ]

• Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu. Adaptive Cluster Throttling: Improving High-Load Performance in Bufferless On-Chip Networks. SAFARI Technical Report No. 2011-006. September 6, 2011.

  [ pdf ]

• George Nychis, Chris Fallin, Thomas Moscibroda, Srinivasan Seshan, Onur Mutlu. Congestion Control for Scalability in Bufferless On-Chip Networks. SAFARI Technical Report No. 2011-003.

  [ pdf ]

• Chris Fallin, Chris Craik, Onur Mutlu. CHIPPER: A Low-complexity Bufferless Deflection Router. SAFARI Technical Report No. 2010-001.

  [ pdf ]

  (this is an extended version of our HPCA 2011 paper above.)